Hardware-Based Data Prefetching

Jean-Loup Baer
Department of Computer Science and Engineering
University of Washington
Seattle, Washington

The performance of a hardware function unit whose goal is to assist a data cache in prefetching data accesses, so that memory latency is hidden as often as possible, was described and evaluated. The motivation for this work is the hypothesis that memory latency and bandwidth are progressing at a much slower pace than processor performance. The basic idea of the prefetching scheme was to keep track of data access patterns in a reference prediction table organized as an instruction cache. Three variations of the design were evaluated by simulating ten SPEC benchmarks on a cycle-by-cycle basis. The results showed that hardware prefetching can yield significant reductions in the data access penalty when compared with regular caches.