Christoffer Amlo, Graduate Student Researcher
Robert Glamm, Graduate Student Researcher
Chris J. Hescott, Undergraduate Student Researcher
Timothy L. Holston, Undergraduate Student Researcher
Jian Huang, Graduate Student Researcher
Iffat Kazi, Graduate Student Researcher
Kelly Seabold, Undergraduate Student Researcher
Qing Zhao, Graduate Student Researcher
Cody Zilverberg, Supercomputing Institute Undergraduate Intern
99/1 |
"Techniques for Obtaining High Performance in Java Programs," I.H. Kazi, B. Stanley, D.J. Lilja, A. Verma, and S. Davis, University of Minnesota Supercomputing Institute Research Report UMSI 99/1, January 1999. Publication in press. |
99/2 |
"Education at a Distance: A Report from the Front," D.J. Lilja, in Workshop on Computer Architecture Education (WCAE), International Symposium on High-Performance Computer Architecture (HPCA), 1999. |
99/62 |
"Dimensions of Verifying the Hardware-Software Interface in a Shared-Memory Multiprocessor," D. Abts, D.J. Lilja, A. Bataineh, and S. Scott, University of Minnesota Supercomputing Institute Research Report UMSI 99/62, April 1999. Publication in press. |
99/90 |
"A Compiler-Assisted Data Prefetch Controller," S. VanderWiel, D.J. Lilja, in International Conference on Computer Design (October, 1999) p. 372. |
99/184 |
"A Balanced Approach to High-Level Verification: Performance Trade-offs in Verifying Large-Scale Multiprocessors," D. Abts, M. Roberts, and D.J. Lilja, University of Minnesota Supercomputing Institute Research Report UMSI 99/184, October 1999. Publication in press. |
In building new generations of microprocessors with ever higher performance, CPU designers always face two major challenges. The first is to tackle the scalability issue when increasing the number of instructions issued per machine cycle (IPC) while simultaneously shortening the clock cycle time. The second challenge is to bridge the worsening "speed gap" between the processor and its memory. These researchers have previously proposed the superthreaded processor architecture to address these challenges by exploiting more sources of parallelism in application programs through both instruction-level and thread-level speculation with compiler-assisted cross-thread runtime data dependence checking. One of the main goals of this project is to develop the new compiler technology needed to support the superthreaded architecture. Preliminary results show excellent potential for reducing application execution time with this architecture, but they also have highlighted the need to more aggressively deal with the memory latency problem. In this current work, a processor simulator is being developed to run in parallel on the IBM SP supercomputer to help validate the superthreaded architecture.
|
|
URL: http://www.msi.umn.edu/about/publications/annualreport/ar2000/depts/IT/EE_CE/lilja.html |
|
| This page last modified on Friday, 30-May-2008 16:14:02 CDT | ||
| Please direct questions or problems to help@msi.umn.edu | ||
|
Website related questions or problems should be directed to
webmaster@msi.umn.edu
The Supercomputing Institute does not collect personal information on visitors to our website. For the University of Minnesota policy, see www.privacy.umn.edu. © 2001 by the Regents of the University of Minnesota |
||