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Research Abstracts Online
January 2008 - March 2009

University of Minnesota Twin Cities
Institute of Technology
Department of Electrical and Computer Engineering

PI: Sachin S. Sapatnekar

Computer-aided Design of VLSI Circuits

These researchers used Supercomputing Institute resources to solve problems in the domain of computer-aided analysis and optimization of very-large-scale integration (VLSI) designs. Specifically, the project addresses problems in the area of topography variation optimization, power grid optimization, and timing analysis.

The first area addresses topography variation on wafers in the manufacturing process, which is one important source of performance degradation and yield loss in nanometer-scale integrated circuit technologies. The group is developing an algorithm for globally routing wires on a chip, considering oxide chemical mechanical polishing (CMP) variations. The next step is to develop full-routing algorithm-considering topography variation in all the stages to further minimize the variation of interlayer dielectric thickness after CMP and to improve the performance and yield; evaluating the routing solutions requires supercomputing capabilities.

The second area considers on-chip decoupling capacitors (decap), a powerful method for suppressing power supply noise in three-dimensional circuits. The researchers are developing an efficient decap-based power grid optimization algorithm to exploit the tradeoff between leakage power and routing congestion using the combination of metal-insulator-metal and complementary metal-oxide-semiconductor decaps. A linear programming (LP) model is built and a standard LP solver (e.g., CPLEX) is required to solve it. The researchers are improving the efficiency of the algorithm so that it can optimize large power grids with millions of nodes.

Finally, with decreasing supply voltages and technology scaling, subthreshold conduction has caused the effect of threshold voltage reduction on temperature to dominate mobility reduction, leading to a decrease in gate delays with temperature, for some output-load input-slope and supply voltage combinations, thereby resulting in a mixed temperature dependence of the circuit delays. The researchers are developing an algorithm that uses the placement information of each block in the circuit, power dissipation, and the temperature distribution on-chip, to determine the maximum temperature-dependent delay of the full-chip paths. An optimization problem is formulated to determine the temperature of each block that results in the maximization of the delay of the full-chip paths, using MSI resources, including CPLEX.

Group Members

Sanjay Kumar, Graduate Student
Yaoguang Wei, Graduate Student
Pingqing Zhou, Graduate Student