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Research Abstracts Online
January 2008 - March 2009

University of Minnesota Twin Cities
Institute of Technology
Department of Computer Science and Engineering

PI: Pen-Chung Yew

Improving Power Efficiency in Heterogeneous Multi-core Processors Using Thread-level Speculation

Current multi-core processors are mainly used for throughput applications and to improve performance in parallel scientific programs. General-purpose applications cannot exploit the multiple cores as the conventional compiler cannot extract threads from these applications due to complex control flow and ambiguous memory accesses. With architecture support for thread-level speculation (TLS), a compiler can aggressively parallelize applications by ignoring ambiguous and infrequent dependences. Recent studies on power efficiency of TLS have shown that depending on the characteristics of the application, a simultaneous multi-threading (SMT) or chip multi-processor (CMP) architecture can be more efficient. In this project, the researchers exploit this behavior by using a heterogeneous multi-core architecture. The heterogeneous multi-core would contain a heavy core with SMT support and a few lightweight cores (CMP). Depending on the characteristics of a particular loop the heavy core or the lightweight cores would be selected to optimize the efficiency of the entire application. The researchers are studying different selection strategies to optimize performance, power and energy-delay product.

Group Members

Venkatesan Packirisamy, Graduate Student
Yangchun Yuo, Graduate Student