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Sapatnekar_SS

Research Abstracts Online
January 2009 - March 2010

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University of Minnesota Twin Cities
Institute of Technology
Department of Electrical and Computer Engineering

PI: Sachin S. Sapatnekar

Computer-aided Design of VLSI Circuits

These researchers used MSI resources to solve problems in the domain of computer-aided analysis and optimization of very-large-scale integration (VLSI) designs. Specifically, the project addresses problems in the area of three-dimensional network-on-chip (NoC) design, topography variation optimization, power grid optimization, and timing analysis, the features of which are described below.

NoCs have been proposed as a scalable solution to the global communication challenges in System-on-Chip (SoC) design. Three-dimensional integration technology, in which multiple tiers are stacked above each other and vertically connected using through-silicon vias (TSVs), has provided new opportunities for NoC architecture design. These researchers have proposed a floorplan-aware three-dimensional NoC synthesis algorithm for application-specific NoC design problems, based on a multicommodity flow (MCF) network formulation.

Topography variation on wafers in the manufacturing process is one important source of performance degradation and yield loss in nanometer-scale integrated circuit technologies. The group is developing an algorithm for globally routing wires on a chip, considering oxide chemical mechanical polishing (CMP) variations. The next step is to develop full-routing algorithm-considering topography variation in all the stages to further minimize the variation of interlayer dielectric thickness after CMP and to improve the performance and yield.

Finally, dynamic power consumption is increasing enormously in high performance processors today, owing to the high frequencies of operation. Dynamic Voltage and Frequency Scaling (DVFS) is a way to save wasteful power consumption by reducing frequency and supply voltage of processor when the processor is doing operations that are not bound by the speed of operation of the processor core but rather limited by the slower peripherals attached to processor. The researchers are looking at such a DVFS system for a multi-core processor. They intend to cluster multiple cores of a multi-core processor into voltage domains and apply DVFS on the voltage domain rather than on a per-core basis as this has been found to be optimal.

Group Members

Tejaswini Kolpe, Graduate Student
Sanjay Kumar, Graduate Student
Yaoguang Wei, Graduate Student
Pingqing Zhou, Graduate Student