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Research Abstracts Online
January 2010 - March 2011

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University of Minnesota Twin Cities
College of Science and Engineering
Department of Electrical and Computer Engineering

PI: Sachin S. Sapatnekar

Computer-Aided Design of VLSI Circuits

These researchers use MSI resources to solve problems in the domain of computer-aided analysis and optimization of very-large-scale integration (VLSI) designs. Specifically, the project addresses problems in the areas of process variation modeling, power delivery for chip multiprocessor systems, and dynamic voltage and frequency scaling optimization, the features of which are described below.

In nanometer-scale integrated circuit technologies, rapid thermal annealing (RTA)-induced variation on wafers in the manufacturing process is one important source of performance degradation and yield loss. RTA-induced variation is largely determined by the annealing temperature variation on the wafer. To evaluate and then minimize the impact of the RTA-induced variations before manufacturing, accurate and efficient thermal modeling is necessary. In this work, the researchers are developing accurate and efficient thermal modeling to obtain the temperature distribution on the surface of the wafer in the annealing process. MSI resources are used for model verification.

The second focus area concerns power delivery for multicore processors. A multicore system faces power-delivery challenges, which can be overcome by a strategy of simultaneously leveraging a design and CAD approach to solve the problem. The researchers are developing an appropriate power delivery network model and solving the full chip level analysis and optimization for advanced multicore systems with large power grids that could contain millions of nodes. The computational needs of this project necessitate MSI resources.

Finally, dynamic power consumption is increasing enormously in high performance processors today, owing to the high frequencies of operation. Dynamic Voltage and Frequency Scaling (DVFS) is a way to save wasteful power consumption by reducing frequency and supply voltage of processor when the processor is doing operations that are not bound by the speed of operation of the processor core but rather limited by the slower peripherals attached to processor. The researchers are looking at such a DVFS system for a multi-core processor. They intend to cluster multiple cores of a multi-core processor into voltage domains and apply DVFS on the voltage domain rather than on a per-core basis as this has been found to be optimal.

Group Members

Tejaswini Kolpe, Graduate Student
Yaoguang Wei, Graduate Student
Pingqing Zhou, Graduate Student