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SaptanekarSS

Research Abstracts Online
January - December 2011

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University of Minnesota Twin Cities
College of Science and Engineering
Department of Electrical and Computer Engineering

PI: Sachin S. Sapatnekar

Computer-Aided Design of VLSI Circuits

These researchers use MSI resources to solve problems in the domain of computer-aided analysis and optimization of very-large-scale integration (VLSI) designs. Specifically, the project addresses problems in the areas of Network-on-Chip design for chip multiprocessor systems, topography variation optimization, dynamic-voltage and frequency-scaling optimization, and the effects of through-silicon vias on circuit behavior, as described below.

The first focus area is a Network-on-Chip (NoC) design for chip multiprocessor (CMP) systems. The emergence of CMP systems has placed a great focus on the design of on-chip communication structures. NoCs, composed of switches and links, have been proposed as a scalable solution to the global on-chip communication challenges. These researchers are developing approaches to build customized NoCs that are specifically tailored for CMP systems. This work is based on a floorplan-aware, application-specific NoC synthesis algorithm using multicommodity flow (MCF) network formulation. MSI resources are necessary to efficiently solve the MCF problem.

The second area concerns a topography-variation-aware routing algorithm. In nanometer-scale integrated circuit technologies, topography variation on wafer in manufacturing process is one important source of performance degradation and yield loss. The researchers are developing algorithms for routing wires on a chip, considering chemical mechanical polishing (CMP) variations. In the next phase of the project, they intend to develop a global routing algorithm considering topography variation induced by copper CMP and to improve the performance and yield. To evaluate the routing solutions, the amount of dummy fill that must be inserted is required to be computed using MSI resources.

A third area involves dynamic power consumption, which is increasing enormously in high-performance processors today, owing to the high frequencies of operation. Dynamic Voltage and Frequency Scaling (DVFS) is a way to save wasteful power consumption by reducing frequency and supply voltage of processor when the processor is doing operations that are not bound by the speed of operation of the processor core but rather limited by the slower peripherals attached to processor. These researchers are looking at such a DVFS system for a multi-core processor. They intend to cluster multiple cores of a multi-core processor into voltage domains and apply DVFS on the voltage domain rather than on a per-core basis as this has been found to be optimal. MSI resources are very helpful to solve the involved optimization problems.

Finally, three-dimensional integrated circuits are an emerging technology paradigm where multiple layers of conventional two-dimensional circuits are stacked over each other, with through-silicon vias (TSVs) used to connect the layers. TSVs introduce thermal stress into the silicon die, which in turn causes electrical changes due to piezoresistive effects. This project studies the effects of TSVs on circuit behavior.

Group Members

Sravan Marella, Graduate Student
Yaoguang Wei, Graduate Student
Pingqing Zhou, Graduate Student