Computer-Aided Design of VLSI Circuits


Computer-Aided Design of VLSI Circuits

These researchers use MSI supercomputing resources to solve problems in the domain of computer-aided analysis and optimization of VLSI designs. Specifically, the projects will address two problems described below.

  • Impact of thermal-mechanical effects on circuit performance in sub-micron planar and 3D-IC technologies: In 3D-IC technology, dies are stacked vertically and thick cylindrical shaped copper pillars (through silicon vias, TSVs) are used to connect the circuits on different layers. During manufacturing, both silicon and copper TSVs undergo annealing process with a temperature ramp from 250 degrees down to room temperature. However, due to the coefficient of thermal expansion (CTE) mismatch between copper and silicon, thermal residual stress develops inside silicon that impacts the transistor electrical properties and thereby system timing performance. This project is looking into methods for modeling these effects and capturing their impact on circuit performance. In addition, the researchers are also developing modeling and optimization methods for new transistor structures called FinFETs that use a fully three-dimensional structure along with intentional stressors inserted to enhance performance.
  • Electromigration-aware power delivery network analysis: Electromigration has become a serious reliability issue while designing VLSI circuits in current technologies. There is a growing need to accurately model the effects of electromigration and then use this model within the design flow of VLSI circuits. Current models for electromigration are simple and inaccurate, and these researchers aim to come up with electromigration model for the interconnects (metal wires) in the power delivery network that is computationally efficient while physically accurate, and further apply the model to analyze the power delivery network, which typically has hundreds of thousands of metal wires for a single chip. Electromigration is also intimately linked with on-chip residual stress due to CTE mismatches between various constituents of the chip, as well as the stress build-up due to the gradient of atomic concentration. The goal of this project is to analyze the impact of these effects.

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