Parallel Simulations for Computer Architecture and Computer Aided Design

<h3 class="red">Parallel Simulations for Computer Architecture and Computer Aided Design</h3><p>For several emerging applications such as wearables, internet of things, and sensor networks, energy efficiency is of utmost importance. While custom ASICs have higher energy efficiency, general-purpose embedded processors are the preferred solution for many such applications due to the evolving nature of these applications and the high costs of custom IC design. The Sartori group discovers and exploits new opportunities for improving energy efficiency in general purpose embedded processors. They are currently focusing on new opportunities for energy efficiency enabled by detailed co-analysis of the design-level description of a processor and an application binary. Traditionally, co-analysis of the low-level hardware and details for a system has not been performed due to prohibitive costs. However, this group has developed anutomated analysis tools that perform unique analyses and expose new opportunities for energy efficiency. A few of their ongoing projects in this area are described below.</p><ul><li>The group has created a tool that identifies the parts of a processor that can never be exercised by a particular application. As such, they can identify paths in a processor that can never be exercised for a particular workload. If the most critical paths in a processor are not exercised, then extra timing slack exists that can be exploited to reduce power or increase performance.</li><li>Knowing the parts of a processor that can never be exercised by an application or application phase also allows new opportunities for aggressive power gating. The researchers are developing techniques that allow the benefits of aggressive hardware-based power gating with costs similar to those of software power gating. Their techniques can provide guarantees that power gating decisions are safe without requiring hardware checking mechanisms and provide near-optimal power savings, compared to oracular control decisions.</li><li>Detailed activity analysis and guarantees for a hardware-software system can also allow researchers to more accurately and aggressively bound the peak power requirements of the system. The gap between conventional peak power rating and application-aware peak power rating can be exploited for reduced energy and area, improved performance and throughput, and greater efficiency.</li></ul><p>The new techniques this group is creating require detailed analysis of a system&#39;s hardware and software. This detailed analysis relies on high-throughput parallel simulation methodologies to be performed in a reasonable amount of time. As such, it relies on high-performance parallel computing resources.</p><p>Return to this PI&#39;s <a href="">main page</a>.</p><p>&nbsp;</p>
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