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Tutorial Registration: Basic PHI tutorial

Date: Thursday, December 19, 2013, 01:00 pm - 04:00 pm
Location: 575 Walter
Instructor(s): Brent Swartz, MSI, Evan F Bollig PhD, University of Minnesota

The Intel Xeon PHI accelerator was recently released, and MSI now has PHI nodes available to users in the phi queue on cascade. This tutorial will provide the basic information needed to: 1. Explain the hardware of the Intel PHI. 2. Determine whether the PHI coprocessor could be beneficial for their application's performance. 3. Port their codes to use the Intel PHI, using native or offload mode. 4. Explain how to optimize the performance of a code for the PHI coprocessor. 5. Use the PHI in offload mode for relevant MKL routines. 6. Give an example of a code that uses the PHI to achieve performance gains.

Prerequisites: Knowledge of C, C++, or Fortran programming. Knowledge of OpenMP
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